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» Simulation of Soliton Circuits
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ISLPED
2009
ACM
127views Hardware» more  ISLPED 2009»
14 years 4 months ago
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic
In this paper, we observe that minimum energy Emin of subthreshold logic dramatically increases when reaching 45 nm node. We demonstrate by circuit simulation and analytical model...
David Bol, Dina Kamel, Denis Flandre, Jean-Didier ...
SLIP
2009
ACM
14 years 4 months ago
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim
DATE
2008
IEEE
131views Hardware» more  DATE 2008»
14 years 4 months ago
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints
Sleep transistor insertion is one of today’s most promising and widely adopted solutions for controlling stand-by leakage power in nanometer circuits. Although single-cycle powe...
Andrea Calimera, Luca Benini, Enrico Macii
ISCAS
2008
IEEE
104views Hardware» more  ISCAS 2008»
14 years 4 months ago
An offset compensation technique for bandgap voltage reference in CMOS technology
— A precision integrated bandgap voltage reference in 0.35μm CMOS technology is here presented. The circuit uses natural npn bipolar transistors as reference diodes. A particula...
Stefano Ruzza, Enrico Dallago, Giuseppe Venchi, Se...
GLVLSI
2007
IEEE
187views VLSI» more  GLVLSI 2007»
14 years 4 months ago
DAG based library-free technology mapping
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
Felipe S. Marques, Leomar S. da Rosa Jr., Renato P...