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» Simulation of Soliton Circuits
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DAC
2012
ACM
12 years 14 days ago
Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs
In this work, we propose a fast and accurate chip/package thermomechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also present a design optimization meth...
Moongon Jung, David Z. Pan, Sung Kyu Lim
HPCA
2004
IEEE
14 years 10 months ago
Exploiting Prediction to Reduce Power on Buses
We investigate coding techniques to reduce the energy consumed by on-chip buses in a microprocessor. We explore several simple coding schemes and simulate them using a modified Si...
Victor Wen, Mark Whitney, Yatish Patel, John Kubia...
ICCD
2005
IEEE
116views Hardware» more  ICCD 2005»
14 years 7 months ago
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit ...
Fei Hu, Vishwani D. Agrawal
ISQED
2008
IEEE
85views Hardware» more  ISQED 2008»
14 years 4 months ago
A Statistic-Based Approach to Testability Analysis
This paper presents a statistic-based approach for evaluating the testability of nodes in combinational circuits. This testability measurement is obtained via Monte Carlo simulati...
Chuang-Chi Chiou, Chun-Yao Wang, Yung-Chih Chen
FPL
1999
Springer
103views Hardware» more  FPL 1999»
14 years 2 months ago
IP Validation for FPGAs Using Hardware Object Technology
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...
Steve Casselman, John Schewel, Christophe Beaumont