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CORR
2010
Springer
197views Education» more  CORR 2010»
13 years 10 months ago
Modelling of Human Glottis in VLSI for Low Power Architectures
The Glottal Source is an important component of voice as it can be considered as the excitation signal to the voice apparatus. Nowadays, new techniques of speech processing such a...
Nikhil Raj, R. K. Sharma
IJON
2007
118views more  IJON 2007»
13 years 10 months ago
Low power CMOS electronic central pattern generator design for a biomimetic underwater robot
— This paper, presents a feasability study of a central pattern generator-based analog controller for an autonomous robot. The operation of a neuronal circuit formed of electroni...
Young-Jun Lee, Jihyun Lee, Kyung Ki Kim, Yong-Bin ...
TCAD
2008
93views more  TCAD 2008»
13 years 10 months ago
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
ICCD
2004
IEEE
112views Hardware» more  ICCD 2004»
14 years 7 months ago
An Infrastructure IP for On-Chip Clock Jitter Measurement
In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two differe...
Jui-Jer Huang, Jiun-Lang Huang
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
14 years 7 months ago
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
Mihir R. Choudhury, Quming Zhou, Kartik Mohanram