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IOLTS
2007
IEEE
155views Hardware» more  IOLTS 2007»
14 years 3 months ago
On Derating Soft Error Probability Based on Strength Filtering
— Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies and the trend is expected to get worse. A significant frac...
Alodeep Sanyal, Sandip Kundu
ISCAS
2003
IEEE
131views Hardware» more  ISCAS 2003»
14 years 2 months ago
Process variation dimension reduction based on SVD
We propose an algorithm based on singular value decomposition (SVD) to reduce the number of process variation variables. With few process variation variables, fault simulation and...
Zhuo Li, Xiang Lu, Weiping Shi
FPGA
1999
ACM
139views FPGA» more  FPGA 1999»
14 years 1 months ago
Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs
The demand for high-speed FPGA compilation tools has occurred for three reasons: first, as FPGA device capacity has grown, the computation time devoted to placement and routing h...
Yaska Sankar, Jonathan Rose
DAC
2009
ACM
14 years 10 months ago
A robust and efficient harmonic balance (HB) using direct solution of HB Jacobian
In this paper we introduce a new method of performing direct solution of the harmonic balance Jacobian. For examples with moderate number of harmonics and moderate to strong nonli...
Amit Mehrotra, Abhishek Somani
DAC
2007
ACM
14 years 10 months ago
Global Critical Path: A Tool for System-Level Timing Analysis
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...