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DATE
2003
IEEE
120views Hardware» more  DATE 2003»
14 years 2 months ago
Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step
Abstract — This paper defines a new diagnosis problem for diagnosing delay defects based upon statistical timing models. We illustrate the differences between the delay defect d...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-...
ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
14 years 2 months ago
A novel improvement technique for high-level test synthesis
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jaha...
ISCAS
2003
IEEE
90views Hardware» more  ISCAS 2003»
14 years 2 months ago
A reduction technique of large scale RCG interconnects in complex frequency domain
High frequency digital LSIs usually consist of many subcircuits coupled with multi-conductor interconnects embedded in the substrate. They sometimes cause serious problems of the ...
Yoshihiro Yamagami, Yoshifumi Nishio, Atsumi Hatto...
ISCAS
2003
IEEE
172views Hardware» more  ISCAS 2003»
14 years 2 months ago
Performance modeling of resonant tunneling based RAMs
Tunneling based random-access memories (TRAM’s) have recently garnered a great amount of interests among the memory designers due to their intrinsic merits such as reduced power...
Hui Zhang, Pinaki Mazumder, Li Ding 0002, Kyoungho...
VTS
2003
IEEE
89views Hardware» more  VTS 2003»
14 years 2 months ago
Diagnosis of Delay Defects Using Statistical Timing Models
— In this paper, we study the problem of delay defect diagnosis based on statistical timing models. We propose a diagnosis algorithm that can effectively utilize statistical timi...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-...