1304 search results - page 211 / 261 » Simulation of Soliton Circuits |
DAC
2004
ACM
14 years 9 months ago
2004
ACM
We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than ...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Existing approaches to timing analysis under uncertainty are based on restrictive assumptions. Statistical STA techniques assume that the full probabilistic distribution of parame...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
Most existing buffering algorithms neglect the impact of inductance on circuit performance, which causes large error in circuit analysis and optimization. Even for the approaches...
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
Abstract— We present in this paper a new interconnect-driven multilevel floorplanning, called IMF, to handle large-scale building-module designs. Unlike the traditional multilev...
SAC
2006
ACM
14 years 2 months ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...