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ICC
2008
IEEE
126views Communications» more  ICC 2008»
14 years 3 months ago
Backlog Aware Scheduling for Large Buffered Crossbar Switches
—A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with i...
Aditya Dua, Benjamin Yolken, Nicholas Bambos, Wlad...
ISQED
2008
IEEE
186views Hardware» more  ISQED 2008»
14 years 3 months ago
Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
Foad Dabiri, Navid Amini, Mahsan Rofouei, Majid Sa...
ISQED
2008
IEEE
119views Hardware» more  ISQED 2008»
14 years 3 months ago
Instruction Scheduling for Variation-Originated Variable Latencies
The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay also has variat...
Toshinori Sato, Shingo Watanabe
MICRO
2008
IEEE
88views Hardware» more  MICRO 2008»
14 years 3 months ago
Facelift: Hiding and slowing down aging in multicores
Processors progressively age during their service life due to normal workload activity. Such aging results in gradually slower circuits. Anticipating this fact, designers add timi...
Abhishek Tiwari, Josep Torrellas
PIMRC
2008
IEEE
14 years 3 months ago
BER analysis of single-carrier MPAM in the presence of ADC quantization noise
— Noisy radio frequency (RF) circuits tend to degrade the system performance, especially in high frequency communication systems. The performance analysis of such systems is norm...
Umar H. Rizvi, Gerard J. M. Janssen, Jos H. Weber