Sciweavers

1304 search results - page 223 / 261
» Simulation of Soliton Circuits
Sort
View
VTS
2008
IEEE
77views Hardware» more  VTS 2008»
14 years 3 months ago
Test-Pattern Ordering for Wafer-Level Test-During-Burn-In
—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
CEC
2007
IEEE
14 years 3 months ago
Evolving neuromodulatory topologies for reinforcement learning-like problems
— Environments with varying reward contingencies constitute a challenge to many living creatures. In such conditions, animals capable of adaptation and learning derive an advanta...
Andrea Soltoggio, Peter Dürr, Claudio Mattius...
GLVLSI
2007
IEEE
114views VLSI» more  GLVLSI 2007»
14 years 3 months ago
Design of mixed gates for leakage reduction
Leakage power dissipation is one of the most critical factors for the overall current dissipation and future designs. However, design techniques for the reduction of leakage power...
Frank Sill, Jiaxi You, Dirk Timmermann
IJCNN
2007
IEEE
14 years 3 months ago
Implementation of multi-layer leaky integrator networks on a cellular processor array
- We present an application of a massively parallel processor array VLSI circuit to the implementation of neural networks in complex architectural arrangements. The work was motiva...
David R. W. Barr, Piotr Dudek, Jonathan M. Chamber...
ISQED
2007
IEEE
236views Hardware» more  ISQED 2007»
14 years 3 months ago
3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function Method
Due to the roaring power dissipation and gaining popularity of 3D integration, thermal dissipation has been a critical concern of modern VLSI design. The availability for chip-lev...
Dongkeun Oh, Charlie Chung-Ping Chen, Yu Hen Hu