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ISVLSI
2007
IEEE
121views VLSI» more  ISVLSI 2007»
16 years 8 days ago
Performance of Graceful Degradation for Cache Faults
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchit...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
154
Voted
ISVLSI
2007
IEEE
121views VLSI» more  ISVLSI 2007»
16 years 8 days ago
Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor
Power line communications (PLC) using impulse ultra wideband (UWB) in a microprocessor had been proposed for ubiquitous access of internal nodes for test/debug purposes. In this p...
Rajesh Thirugnanam, Dong Sam Ha, T. M. Mak
168
Voted
VTC
2007
IEEE
16 years 8 days ago
Discrete Power Allocation for Lifetime Maximization in Cooperative Networks
Abstract— Discrete power allocation strategies for amplifyand-forward cooperative networks are proposed based on selective relaying methods. The goal of power allocation is to ma...
Wan-Jen Huang, Yao-Win Hong, C. C. Jay Kuo
VTS
2007
IEEE
129views Hardware» more  VTS 2007»
16 years 7 days ago
Supply Voltage Noise Aware ATPG for Transition Delay Faults
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
ISNN
2007
Springer
16 years 4 days ago
Hybrid Intelligent Modeling Approach for the Ball Mill Grinding Process
Modeling for the ball mill grinding process is still an imperative but difficult problem for the optimal control of mineral processing industry. Due to the integrated complexities ...
Ming Tie, Jing Bi, Yushun Fan