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ISPD
2006
ACM
126views Hardware» more  ISPD 2006»
14 years 2 months ago
Noise driven in-package decoupling capacitor optimization for power integrity
The existing decoupling capacitance optimization approaches meet constraints on input impedance for package. In this paper, we show that using impedance as constraints leads to la...
Jun Chen, Lei He
CODES
2005
IEEE
14 years 2 months ago
A power estimation methodology for systemC transaction level models
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
Nagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan
DSD
2005
IEEE
75views Hardware» more  DSD 2005»
14 years 2 months ago
An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform
We describe a new e-learning environment and a runtime platform for educational tools on digital system testing and design for testability. This environment is being developed in ...
Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogub...
DSN
2005
IEEE
14 years 2 months ago
Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files
Register files are in the critical path of most high-performance processors and their latency is one of the most important factors that limit their size. Our goal is to develop er...
Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, ...
ISCAS
2005
IEEE
224views Hardware» more  ISCAS 2005»
14 years 2 months ago
A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter
— A new operation mode using a partially depleted hybrid lateral BJT-CMOS inverter on SOI, named as a new unified-BiCMOS (U-BiCMOS) inverter, is proposed. The scheme utilizes the...
Toshiro Akino, Kei Matsuura, Akiyoshi Yasunaga