— In many verification tools methods for functional simulation based on reduced ordered Binary Decision Diagrams (BDDs) are used. The evaluation time for a BDD can be crucial an...
— This paper presents a SAT-based ATPG tool targeting on a path-oriented transition fault model. Under this fault model, a transition fault is detected through the longest sensit...
This paper presents a fault tolerant design technique for the clockless wave pipeline. The specific architectural model investigated in this paper is the two-phase clockless asyn...
T. Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yon...
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low po...
CMOS gates consume different amounts of power whether their output has a falling or a rising edge. Therefore the overall power consumption of a CMOS circuit leaks information about...
Sylvain Guilley, Philippe Hoogvorst, Renaud Pacale...