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» Simulation of Soliton Circuits
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ASPDAC
2004
ACM
107views Hardware» more  ASPDAC 2004»
14 years 2 months ago
Minimization of the expected path length in BDDs based on local changes
— In many verification tools methods for functional simulation based on reduced ordered Binary Decision Diagrams (BDDs) are used. The evaluation time for a BDD can be crucial an...
Rüdiger Ebendt, Wolfgang Günther, Rolf D...
ASPDAC
2004
ACM
102views Hardware» more  ASPDAC 2004»
14 years 2 months ago
TranGen: a SAT-based ATPG for path-oriented transition faults
— This paper presents a SAT-based ATPG tool targeting on a path-oriented transition fault model. Under this fault model, a transition fault is detected through the longest sensit...
Kai Yang, Kwang-Ting Cheng, Li-C. Wang
CF
2004
ACM
14 years 2 months ago
Fault tolerant clockless wave pipeline design
This paper presents a fault tolerant design technique for the clockless wave pipeline. The specific architectural model investigated in this paper is the two-phase clockless asyn...
T. Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yon...
ISLPED
2004
ACM
124views Hardware» more  ISLPED 2004»
14 years 2 months ago
The design of a low power asynchronous multiplier
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low po...
Yijun Liu, Stephen B. Furber
CARDIS
2004
Springer
149views Hardware» more  CARDIS 2004»
14 years 2 months ago
Differential Power Analysis Model and Some Results
CMOS gates consume different amounts of power whether their output has a falling or a rising edge. Therefore the overall power consumption of a CMOS circuit leaks information about...
Sylvain Guilley, Philippe Hoogvorst, Renaud Pacale...