1304 search results - page 236 / 261 » Simulation of Soliton Circuits |
ISCAS
1999
IEEE
13 years 12 months ago
1999
IEEE
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
VLSID
1999
IEEE
13 years 12 months ago
1999
IEEE
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
ASYNC
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs a...
VLSID
1997
IEEE
13 years 11 months ago
1997
IEEE
Cascode CMOS op-amps use a large number of external bias voltages. This results in numerous drawbacks, namely, an area and power overhead, susceptiblity of the bias lines to noise...
ISLPED
1997
ACM
13 years 11 months ago
1997
ACM
In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RTlevel power analysis. The proposed macro-model predicts not only...