14 search results - page 3 / 3 » Simultaneous Analytic Area and Power Optimization for Repeat... |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...
WD
2010
13 years 5 months ago
2010
: In this paper we use an analytical model to study how two radio networks : a primary network and a secondary network can coexist within the same area. We use a very simple protoc...