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ICPADS
2006
IEEE
15 years 10 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
ASPDAC
1998
ACM
101views Hardware» more  ASPDAC 1998»
15 years 8 months ago
An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits
ABSTRACT - This paper presents a new design flow, FPDSiMPA, and a set of techniques for synthesizing high-performance sub-half micron logic circuits. FPD-SiMPA consists of logic p...
Jinan Lou, Amir H. Salek, Massoud Pedram
CSDA
2006
84views more  CSDA 2006»
15 years 4 months ago
Three-mode partitioning
The three-mode partitioning model is a clustering model for three-way three-mode data sets that implies a simultaneous partitioning of all three modes involved in the data. In the...
Jan Schepers, Iven Van Mechelen, Eva Ceulemans
ICPR
2008
IEEE
15 years 10 months ago
A new multiobjective simulated annealing based clustering technique using stability and symmetry
Most clustering algorithms operate by optimizing (either implicitly or explicitly) a single measure of cluster solution quality. Such methods may perform well on some data sets bu...
Sriparna Saha, Sanghamitra Bandyopadhyay
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
15 years 8 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar