78 search results - page 10 / 16 » Simultaneous buffer and wire sizing for performance and powe... |
DAC
1997
ACM
13 years 11 months ago
1997
ACM
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
ICC
2007
IEEE
14 years 1 months ago
2007
IEEE
— The analysis regarding the impact of the single-step power control (SSPC) scheme on the system performance such as bit error rate, packet error rate and queueing variation is h...
ISLPED
2003
ACM
14 years 20 days ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
TWC
2008
13 years 7 months ago
2008
In this paper a single-input-single-output wireless data transmission system with adaptive modulation and coding over correlated fading channel is considered, where run-time power ...
ISLPED
2005
ACM
14 years 29 days ago
2005
ACM
This paper addresses the problem of low-power fanout optimization with multiple threshold voltage inverters. Introducing splitting and merging conversions that preserve delay, pow...