78 search results - page 7 / 16 » Simultaneous buffer and wire sizing for performance and powe... |
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
ISVLSI
2003
IEEE
14 years 20 days ago
2003
IEEE
The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
We present a fast and efficient combinatorial algorithm to simultaneously identify the candidate locations as well as the sizes of the buffers driving a clock mesh. Due to the hi...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— Recently power becomes a significant issue in clock network design for high-performance ICs because the clock network consumes a large portion of the total power in the whole s...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring...