51 search results - page 7 / 11 » Simultaneous driver and wire sizing for performance and powe... |
DAC
2008
ACM
14 years 8 months ago
2008
ACM
In the design of complex power distribution networks (PDN) with multiple power islands, it is required that the PDN represents a low impedance as seen by the digital modules. This...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics...
JCP
2008
13 years 7 months ago
2008
Rapid increase in transistor density and operating frequency has led to the increase in power densities, exhibiting itself as a high temperature profile. The high temperature spots...
ASPDAC
2009
ACM
13 years 11 months ago
2009
ACM
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
ASPDAC
2005
ACM
14 years 1 months ago
2005
ACM
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...