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    DAC
    2006
    ACM
    148views Computer Architecture» more  DAC 2006»
    Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
    15 years 4 days ago
    Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
    Download  www.ee.ucla.edu
    Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
    Yu Hu, Yan Lin, Lei He, Tim Tuan
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    TODAES
    2008
    69views more  TODAES 2008»
    Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
    13 years 11 months ago
    Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
    Download  www.ee.ucla.edu
    Yu Hu, Yan Lin, Lei He, Tim Tuan
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    DAC
    2005
    ACM
    111views Computer Architecture» more  DAC 2005»
    Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
    15 years 4 days ago
    Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
    Download  eda.ee.ucla.edu
    To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in ...
    Yan Lin, Lei He
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    ISPD
    2006
    ACM
    84views Hardware» more  ISPD 2006»
    Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization
    14 years 5 months ago
    Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization
    Download  www.gtcad.gatech.edu
    The integration of retiming and simultaneous supply/threshold voltage scaling has a potential to enable more rigorous total power reduction. However, such integration is a highly ...
    Mongkol Ekpanyapong, Sung Kyu Lim
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