67 search results - page 4 / 14 » Simultaneously improving code size, performance, and energy ... |
ASPDAC
2004
ACM
14 years 23 days ago
2004
ACM
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...
LCTRTS
2010
Springer
13 years 5 months ago
2010
Springer
The issues of compiler optimization phase ordering and selection present important challenges to compiler developers in several domains, and in particular to the speed, code size,...
VLSID
2005
IEEE
14 years 7 months ago
2005
IEEE
This paper presents an RTL generation scheme for a SimpleScalar / PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a p...
ISCA
2003
IEEE
14 years 19 days ago
2003
IEEE
Although adaptive processors can exploit application variability to improve performance or save energy, effectively managing their adaptivity is challenging. To address this probl...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Software implementations of modern block ciphers often require large lookup tables along with code size increasing optimizations like loop unrolling to reach peak performance on g...