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» Single-rail handshake circuits
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CASES
2007
ACM
14 years 16 days ago
Performance-driven syntax-directed synthesis of asynchronous processors
The development of robust and efficient synthesis tools is important if asynchronous design is to gain more widespread acceptance. Syntax-directed translation is a powerful synthe...
Luis A. Plana, Doug A. Edwards, Sam Taylor, Luis A...
ENGL
2008
118views more  ENGL 2008»
13 years 8 months ago
Hybrid Architecture of Genetic Algorithm and Simulated Annealing
This paper discusses novel dedicated hardware architecture for hybrid optimization based on Genetic algorithm (GA) and Simulated Annealing (SA). The proposed architecture achieves ...
Masaya Yoshikawa, Hironori Yamauchi, Hidekazu Tera...
MJ
2007
119views more  MJ 2007»
13 years 8 months ago
Automated energy calculation and estimation for delay-insensitive digital circuits
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, ...
FTCS
1994
140views more  FTCS 1994»
13 years 9 months ago
Concurrent Error Detection in Self-Timed VLSI
This paper examines architectural techniques for providing concurrent error detection in self-timed VLSI pipelines. Signal pairs from Differential Cascode Voltage Switch Logic are...
David A. Rennels, Hyeongil Kim
ACSD
2009
IEEE
106views Hardware» more  ACSD 2009»
13 years 6 months ago
Teak: A Token-Flow Implementation for the Balsa Language
This paper describes a new target component set and synthesis scheme for the Balsa asynchronous hardware description language. This new scheme removes the reliance on precise hands...
Andrew Bardsley, Luis A. Tarazona, Doug A. Edwards