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» Sizing Rules for Bipolar Analog Circuit Design
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ICCAD
1998
IEEE
105views Hardware» more  ICCAD 1998»
13 years 11 months ago
Fanout optimization under a submicron transistor-level delay model
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
Pasquale Cocchini, Massoud Pedram, Gianluca Piccin...
DATE
2008
IEEE
75views Hardware» more  DATE 2008»
14 years 2 months ago
Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture
To achieve minimum signal propagation delay, the nonuniform wire width routing architecture has been widely used in modern VLSI design. The non-uniform routing architecture exploi...
Fu-Wei Chen, Yi-Yu Liu
IJON
2007
118views more  IJON 2007»
13 years 7 months ago
Low power CMOS electronic central pattern generator design for a biomimetic underwater robot
— This paper, presents a feasability study of a central pattern generator-based analog controller for an autonomous robot. The operation of a neuronal circuit formed of electroni...
Young-Jun Lee, Jihyun Lee, Kyung Ki Kim, Yong-Bin ...
TCAD
2002
146views more  TCAD 2002»
13 years 7 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier
ICCAD
2000
IEEE
88views Hardware» more  ICCAD 2000»
13 years 12 months ago
Hierarchical Interconnect Circuit Models
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pi...