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ISCA
2011
IEEE
229views Hardware» more  ISCA 2011»
12 years 11 months ago
TLSync: support for multiple fast barriers using on-chip transmission lines
As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament ba...
Jungju Oh, Milos Prvulovic, Alenka G. Zajic
ICCAD
1994
IEEE
119views Hardware» more  ICCAD 1994»
13 years 11 months ago
Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays
We present a new min-cut based placement algorithm for large scale sea-of-gates arrays. In the past all such algorithms used a xed cut line sequence that is determined before min...
Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai...
PATMOS
2005
Springer
14 years 1 months ago
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...
Giorgos Dimitrakopoulos, Dimitris Nikolos
ICDAR
2003
IEEE
14 years 27 days ago
A Line Drawings Degradation Model for Performance Characterization
Line detection algorithms constitute the basis for technical document analysis and recognition. The performance of these algorithms decreases as the quality of the documents degra...
Jian Zhai, Liu Wenyin, Dov Dori, Qing Li
WAN
1998
Springer
13 years 11 months ago
The NRW Metacomputing Initiative
In this paper the Northrhine-Westphalian metacomputing initiative is described. We start by discussing various general aspects of metacomputing and explain the reasons for founding...
Uwe Schwiegelshohn, Ramin Yahyapour