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DATE
2006
IEEE
100views Hardware» more  DATE 2006»
14 years 3 months ago
Heterogeneous behavioral hierarchy for system level designs
Enhancing productivity for designing complex embedded systems requires system level design methodology and language support for capturing complex design in high level models. For ...
Hiren D. Patel, Sandeep K. Shukla, Reinaldo A. Ber...
DSD
2002
IEEE
103views Hardware» more  DSD 2002»
14 years 2 months ago
On the Fundamental Design Gap in Terabit per Second Packet Switching
We discuss the gap we experience in an industrial design path of high-speed packet switches. As bandwidth demand exceeds progress in CMOS technology, system architects are forced ...
M. Verhappen, P. H. A. van der Putten, Jeroen Voet...
ICS
2009
Tsinghua U.
14 years 4 months ago
Towards 100 gbit/s ethernet: multicore-based parallel communication protocol design
Ethernet line rates are projected to reach 100 Gbits/s by as soon as 2010. While in principle suitable for high performance clustered and parallel applications, Ethernet requires ...
Stavros Passas, Kostas Magoutis, Angelos Bilas
VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
14 years 9 months ago
Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
M. S. Gaur, Mark Zwolinski
ICCD
2002
IEEE
146views Hardware» more  ICCD 2002»
14 years 6 months ago
From ASIC to ASIP: The Next Design Discontinuity
A variety of factors is making it increasingly difficult and expensive to design and manufacture traditional Application Specific Integrated Circuits (ASICs). This has started a s...
Kurt Keutzer, Sharad Malik, A. Richard Newton