1859 search results - page 138 / 372 » Sketch-based path design |
ASAP
2007
IEEE
13 years 11 months ago
2007
IEEE
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
CJ
2010
13 years 9 months ago
2010
rder logic (HOL) theorem prover. The high ability of abstraction in the HOL verification system allows its use for the verification task over the whole design path of the circuit, ...
ICCD
2006
IEEE
14 years 6 months ago
2006
IEEE
— We propose a low-leakage register file cell design based on the observation that the physical registers in a superscalar processor have very short life cycles. When a register...
HICSS
2008
IEEE
14 years 3 months ago
2008
IEEE
Architecting security solutions for today’s diverse computer systems is a challenge. The modern business environment is comprised of many different applications, e-mail, databas...
HPCA
1996
IEEE
14 years 1 months ago
1996
IEEE
In this paper, we propose a cache design that provides the same miss rate as a two-way set associative cache, but with a access time closer to a direct-mapped cache. As with other...