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IFIP
1993
Springer
14 years 1 months ago
Self-Timed Architecture of a Reduced Instruction Set Computer
An advanced Self-Timed Reduced Instruction Set Computer (ST-RISC) architecture is described. It is designed hierarchically, and is formally specified functionally at the various ...
Ilana David, Ran Ginosar, Michael Yoeli
ITC
1989
IEEE
70views Hardware» more  ITC 1989»
14 years 1 months ago
The Pseudo-Exhaustive Test of Sequential Circuits
: The concept of a pseudo-exhaustive test for sequential circuits is introduced in a similar way as it is used for combinational networks. Instead of test sets one has to apply pse...
Sybille Hellebrand, Hans-Joachim Wunderlich
DATE
2004
IEEE
125views Hardware» more  DATE 2004»
14 years 1 months ago
Fast Comparisons of Circuit Implementations
Abstract-- Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing ca...
Shrirang K. Karandikar, Sachin S. Sapatnekar
ASPDAC
1995
ACM
110views Hardware» more  ASPDAC 1995»
14 years 1 months ago
Current and charge estimation in CMOS circuits
: CMOS circuits have significant amounts of dynamic short-circuit (or through) current. This can be as large as 20% of the total in well-designed circuits, and up to 80% of the tot...
Sanjay Dhar, Dave J. Gurney
CHI
2005
ACM
13 years 11 months ago
Indirect assessment of web navigation success
Despite much research on hypertext and web navigation, relatively little is known about the relationship between web navigation strategies and success. We present two exploratory ...
Jacek Gwizdka, Ian Spence