Abstract— This paper presents a design environment for efficiently generating application-specific Intellectual Property (IP) cores for system level signal processing algorithm...
Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winse...
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda
In recent years there has been considerable research on automated selection of physical design in database systems. In current solutions, candidate access paths are heuristically ...