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140
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SIPS
2006
IEEE
15 years 9 months ago
Automated Architectural Exploration for Signal Processing Algorithms
Abstract— This paper presents a design environment for efficiently generating application-specific Intellectual Property (IP) cores for system level signal processing algorithm...
Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winse...
131
Voted
DAC
2004
ACM
16 years 4 months ago
A method for correcting the functionality of a wire-pipelined circuit
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
Vidyasagar Nookala, Sachin S. Sapatnekar
153
Voted
DAC
2006
ACM
16 years 4 months ago
An efficient and versatile scheduling algorithm based on SDC formulation
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
Jason Cong, Zhiru Zhang
127
Voted
DAC
2006
ACM
16 years 4 months ago
Rapid estimation of control delay from high-level specifications
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda
216
Voted
SIGMOD
2005
ACM
138views Database» more  SIGMOD 2005»
16 years 3 months ago
Automatic Physical Database Tuning: A Relaxation-based Approach
In recent years there has been considerable research on automated selection of physical design in database systems. In current solutions, candidate access paths are heuristically ...
Nicolas Bruno, Surajit Chaudhuri