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SLIP
2006
ACM
14 years 2 months ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
TCBB
2008
113views more  TCBB 2008»
13 years 8 months ago
Efficient Algorithms for the Computational Design of Optimal Tiling Arrays
The representation of a genome by oligonucleotide probes is a prerequisite for the analysis of many of its basic properties, such as transcription factor binding sites, chromosomal...
Alexander Schliep, Roland Krause
ICCAD
2000
IEEE
188views Hardware» more  ICCAD 2000»
14 years 1 months ago
Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
Sungpack Hong, Taewhan Kim
DFT
1999
IEEE
75views VLSI» more  DFT 1999»
14 years 1 months ago
A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths
Fault identification capabilities are becoming increasingly important in modern designs, not only in support of design debugging methodologies, but also for the purpose of process...
Yiorgos Makris, Alex Orailoglu
ICCAD
2007
IEEE
115views Hardware» more  ICCAD 2007»
14 years 5 months ago
Timing optimization by restructuring long combinatorial paths
—We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We ...
Jürgen Werber, Dieter Rautenbach, Christian S...