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148
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DAC
2003
ACM
15 years 9 months ago
Crosstalk noise in FPGAs
In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem af...
Yajun Ran, Malgorzata Marek-Sadowska
147
Voted
ISCA
2002
IEEE
91views Hardware» more  ISCA 2002»
15 years 8 months ago
Slack: Maximizing Performance Under Technological Constraints
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
Brian A. Fields, Rastislav Bodík, Mark D. H...
137
Voted
SPAA
2010
ACM
15 years 8 months ago
TLRW: return of the read-write lock
TL2 and similar STM algorithms deliver high scalability based on write-locking and invisible readers. In fact, no modern STM design locks to read along its common execution path b...
David Dice, Nir Shavit
130
Voted
VLSID
2000
IEEE
90views VLSI» more  VLSID 2000»
15 years 8 months ago
Performance Analysis of Systems with Multi-Channel Communication Architectures
This paper presents a novel system performance analysis technique to support the design of custom communication architectures for System-on-Chip ICs. Our technique fills a gap in...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
130
Voted
ICFP
2010
ACM
15 years 4 months ago
TeachScheme!: a checkpoint
In 1995, my team and I decided to create an outreach project that would use our research on functional programming to change the K-12 computer science curriculum. We had two diffe...
Matthias Felleisen