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119
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DAC
1996
ACM
15 years 7 months ago
Glitch Analysis and Reduction in Register Transfer Level
: We presentdesign-for-low-power techniques based on glitch reduction for register-transfer level circuits. We analyze the generation and propagation of glitches in both the contro...
Anand Raghunathan, Sujit Dey, Niraj K. Jha
ICRA
1994
IEEE
147views Robotics» more  ICRA 1994»
15 years 7 months ago
Provable Strategies for Vision-Guided Exploration in Three Dimensions
An approach is presented for exploring an unknown, arbitrary surface in three-dimensional (3D) space by a mobile robot. The main contributions are (1) an analysis of the capabilit...
Kiriakos N. Kutulakos, Charles R. Dyer, Vladimir J...
164
Voted
FPGA
1992
ACM
176views FPGA» more  FPGA 1992»
15 years 7 months ago
Minimization of Permuted Reed-Muller Trees for Cellular Logic
The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the truly Cellular Logic. It has been mainly designed for the realization of data path...
Li-Fei Wu, Marek A. Perkowski
115
Voted
ASPDAC
2007
ACM
100views Hardware» more  ASPDAC 2007»
15 years 7 months ago
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong,...
129
Voted
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
15 years 7 months ago
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...
Sanjay Pant, David Blaauw