205 search results - page 15 / 41 » SoC Design and Test Considerations |
GECCO
2003
Springer
13 years 12 months ago
2003
Springer
The aim of the paper is to investigate methods for deriving a suitable set of test paths for a software system. The design and the possible uses of the software system are modelled...
WCE
2007
13 years 7 months ago
2007
Improving testability during the early stages of High-level synthesis has several advantages including reduced test hardware overhead and design iterations. Recently, BIST techniq...
ITC
2003
IEEE
14 years 4 hour ago
2003
IEEE
Today’s low cost wireless phones have driven a need to be able to economically test high volumes of complex RF IC’s at a fraction of the cost of the IC. In June of 2001 the IB...
FPGA
1995
ACM
13 years 10 months ago
1995
ACM
This paper presents a methodology for production-time testing of (uncustomized) segmented channel eld programmable gate arrays (FPGAs) such as those manufactured by Actel [1]. Th...
RSP
2005
IEEE
14 years 9 days ago
2005
IEEE
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...