155 search results - page 21 / 31 » Soft delay error analysis in logic circuits |
DAC
2009
ACM
14 years 8 months ago
2009
ACM
State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing ma...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit ...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
FPL
2008
Springer
13 years 9 months ago
2008
Springer
This paper presents a fast and scalable method of computing signal toggle rate in FPGA-based circuits. Our technique is a vectorless estimation technique, which can be used in a C...
ATS
2003
IEEE
14 years 1 months ago
2003
IEEE
Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error. A test generation methodology, called XGEN, was dev...