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» Soft delay error analysis in logic circuits
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TVLSI
2008
110views more  TVLSI 2008»
13 years 7 months ago
Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits
Abstract--The quantum-dot cellular automata (QCA) model offers a novel nano-domain computing architecture by mapping the intended logic onto the lowest energy configuration of a co...
Sanjukta Bhanja, Sudeep Sarkar
ISCAS
2007
IEEE
173views Hardware» more  ISCAS 2007»
14 years 1 months ago
Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM
— Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upset...
Riaz Naseer, Younes Boulghassoul, Jeff Draper, San...
IOLTS
2007
IEEE
155views Hardware» more  IOLTS 2007»
14 years 2 months ago
On Derating Soft Error Probability Based on Strength Filtering
— Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies and the trend is expected to get worse. A significant frac...
Alodeep Sanyal, Sandip Kundu
ISVLSI
2006
IEEE
129views VLSI» more  ISVLSI 2006»
14 years 1 months ago
Dependability Analysis of Nano-scale FinFET circuits
FinFET technology has been proposed as a promising alternative for deep sub-micro bulk CMOS technology, because of its better scalability. Previous work have studied the performan...
Feng Wang 0004, Yuan Xie, Kerry Bernstein, Yan Luo
ICCAD
2007
IEEE
116views Hardware» more  ICCAD 2007»
14 years 4 months ago
Device and architecture concurrent optimization for FPGA transient soft error rate
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
Yan Lin, Lei He