98 search results - page 7 / 20 » Soft error rate analysis for sequential circuits |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
— In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, Soft Delay Errors (SDE). We define...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Circuits using nano-meter technologies are becoming increasingly vulnerable to signal interference from multiple noise sources as well as radiation-induced soft errors. One way to...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
FPL
2003
Springer
14 years 26 days ago
2003
Springer
DSN
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper concerns the validity of a widely used method for estimating the architecture-level mean time to failure (MTTF) due to soft errors. The method first calculates the fai...