39 search results - page 2 / 8 » Software Pipelining for Coarse-Grained Reconfigurable Instru... |
ASAP
2007
IEEE
13 years 11 months ago
2007
IEEE
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...
ICCAD
1993
IEEE
1993
IEEE
Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors
14 years 1 months ago
— One major problem in pipeline synthesis is the detection and resolution of pipeline hazards. In this paper we present a new solution to the problem in the domain of pipelined a...
DAC
1992
ACM
14 years 1 months ago
1992
ACM
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-softwa...
ERSA
2009
13 years 7 months ago
2009
In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Uni...
ASAP
2000
IEEE
14 years 1 months ago
2000
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...