3667 search results - page 670 / 734 » Software Rejuvenation - Modeling and Analysis |
CODES
2008
IEEE
14 years 3 months ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
CODES
2007
IEEE
14 years 3 months ago
2007
IEEE
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
CODES
2007
IEEE
14 years 3 months ago
2007
IEEE
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
ICS
2007
Tsinghua U.
14 years 2 months ago
2007
Tsinghua U.
Strassen’s matrix multiplication (MM) has benefits with respect to any (highly tuned) implementations of MM because Strassen’s reduces the total number of operations. Strasse...