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CODES
2004
IEEE
14 years 2 months ago
Efficient exploration of on-chip bus architectures and memory allocation
Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and map...
Sungchan Kim, Chaeseok Im, Soonhoi Ha
AMAST
2008
Springer
14 years 19 days ago
A Hybrid Approach for Safe Memory Management in C
In this paper, we present a novel approach that establishes a synergy between static and dynamic analyses for detecting memory errors in C code. We extend the standard C type syste...
Syrine Tlili, Zhenrong Yang, Hai Zhou Ling, Mourad...
TC
2011
13 years 5 months ago
Energy Reduction in Consolidated Servers through Memory-Aware Virtual Machine Scheduling
—Increasing energy consumption in server consolidation environments leads to high maintenance costs for data centers. Main memory, no less than processor, is a major energy consu...
Jae-Wan Jang, Myeongjae Jeon, Hyo-Sil Kim, Heeseun...
ISCA
2006
IEEE
144views Hardware» more  ISCA 2006»
13 years 10 months ago
Conditional Memory Ordering
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
Christoph von Praun, Harold W. Cain, Jong-Deok Cho...
SIGMETRICS
2008
ACM
214views Hardware» more  SIGMETRICS 2008»
13 years 10 months ago
HMTT: a platform independent full-system memory trace monitoring system
Memory trace analysis is an important technology for architecture research, system software (i.e., OS, compiler) optimization, and application performance improvements. Many appro...
Yungang Bao, Mingyu Chen, Yuan Ruan, Li Liu, Jianp...