Sciweavers

2512 search results - page 156 / 503
» Software Transactional Memory
Sort
View
HPCA
2012
IEEE
12 years 6 months ago
System-level implications of disaggregated memory
Recent research on memory disaggregation introduces a new architectural building block—the memory blade—as a cost-effective approach for memory capacity expansion and sharing ...
Kevin T. Lim, Yoshio Turner, Jose Renato Santos, A...
RTSS
2009
IEEE
14 years 5 months ago
Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores
—Memory accesses form an important source of timing unpredictability. Timing analysis of real-time embedded software thus requires bounding the time for memory accesses. Multipro...
Yan Li, Vivy Suhendra, Yun Liang, Tulika Mitra, Ab...
CODES
2001
IEEE
14 years 2 months ago
Retargetable compilation for low power
Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy co...
Wen-Tsong Shiue
ICCD
2007
IEEE
140views Hardware» more  ICCD 2007»
14 years 7 months ago
A low overhead hardware technique for software integrity and confidentiality
Software integrity and confidentiality play a central role in making embedded computer systems resilient to various malicious actions, such as software attacks; probing and tamper...
Austin Rogers, Milena Milenkovic, Aleksandar Milen...
ISCA
2002
IEEE
104views Hardware» more  ISCA 2002»
14 years 3 months ago
Using a User-Level Memory Thread for Correlation Prefetching
This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main ...
Yan Solihin, Josep Torrellas, Jaejin Lee