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ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
14 years 4 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
CGO
2004
IEEE
13 years 11 months ago
Using Dynamic Binary Translation to Fuse Dependent Instructions
Instruction scheduling hardware can be simplified and easily pipelined if pairs of dependent instructions are fused so they share a single instruction scheduling slot. We study an...
Shiliang Hu, James E. Smith
ICECCS
2008
IEEE
203views Hardware» more  ICECCS 2008»
14 years 1 months ago
Using AADL to Model a Protocol Stack
In recent trends, the Architecture Analysis and Design Language (AADL) has received increasing attention from safety-critical software development industries. Specific about the A...
Didier Delanote, Stefan Van Baelen, Wouter Joosen,...
IPPS
2007
IEEE
14 years 1 months ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
ECBS
2009
IEEE
89views Hardware» more  ECBS 2009»
14 years 2 months ago
Optimisation Process for Maintaining Evolvability during Software Evolution
Software systems have to be changed continuously and evolutionarily throughout the whole time of their development and usage. Meanwhile, the software systems have to remain flexi...
Robert Brcina, Stephan Bode, Matthias Riebisch