1406 search results - page 110 / 282 » Software trace cache |
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based ...
CGO
2007
IEEE
14 years 4 months ago
2007
IEEE
Run-time compilation systems are challenged with the task of translating a program’s instruction stream while maintaining low overhead. While software managed code caches are ut...
CASES
2001
ACM
14 years 1 months ago
2001
ACM
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of loc...
IWPC
2002
IEEE
14 years 3 months ago
2002
IEEE
When we try to debug or to comprehend a large program, it is important to separate suspicious program portions from the overall source program. Program slicing is a promising tech...
CASES
2007
ACM
14 years 2 months ago
2007
ACM
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...