Sciweavers

55 search results - page 4 / 11
» Software-based self-test of processors under power constrain...
Sort
View
IPPS
2005
IEEE
14 years 1 months ago
Reducing Power with Performance Constraints for Parallel Sparse Applications
Sparse and irregular computations constitute a large fraction of applications in the data-intensive scientific domain. While every effort is made to balance the computational wor...
Guangyu Chen, Konrad Malkowski, Mahmut T. Kandemir...
ICCD
2007
IEEE
179views Hardware» more  ICCD 2007»
14 years 4 months ago
Energy-aware co-processor selection for embedded processors on FPGAs
In this paper, we present co-processor selection problem for minimum energy consumption in hw/sw co-design on FPGAs with dual power mode. We provide theoretical analysis for the p...
Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Suda...
RSP
2003
IEEE
132views Control Systems» more  RSP 2003»
14 years 20 days ago
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
EURODAC
1995
IEEE
195views VHDL» more  EURODAC 1995»
13 years 11 months ago
A hardware/software partitioning algorithm for pipelined instruction set processor
This paper proposes a new method to design an optimal instruction set for pipelined ASIP development using a formal HW/SW codesign methodology. The codesign task addressed in this...
Binh Ngoc Nguyen, Masaharu Imai, Nobuyuki Hikichi
ISCA
2011
IEEE
269views Hardware» more  ISCA 2011»
12 years 11 months ago
Power management of online data-intensive services
Much of the success of the Internet services model can be attributed to the popularity of a class of workloads that we call Online Data-Intensive (OLDI) services. These workloads ...
David Meisner, Christopher M. Sadler, Luiz Andr&ea...