2647 search results - page 425 / 530 » Solving Term Inequalities |
146
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DAC
2004
ACM
16 years 5 months ago
2004
ACM
Long design cycles due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens...
139
Voted
DAC
2005
ACM
16 years 5 months ago
2005
ACM
In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
144
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DAC
2005
ACM
16 years 5 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
128
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DAC
2006
ACM
16 years 5 months ago
2006
ACM
As a prevalent constraint, sharp slew rate is often required in circuit design which causes a huge demand for buffering resources. This problem requires ultra-fast buffering techn...
163
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DAC
2006
ACM
16 years 5 months ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...