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CASES
2004
ACM
14 years 26 days ago
Balancing design options with Sherpa
Application specific processors offer the potential of rapidly designed logic specifically constructed to meet the performance and area demands of the task at hand. Recently, t...
Timothy Sherwood, Mark Oskin, Brad Calder
VLSID
2002
IEEE
99views VLSI» more  VLSID 2002»
14 years 7 months ago
Input Space Adaptive Embedded Software Synthesis
This paper presents a novel technique, called input space adaptive software synthesis, for the energy and performance optimization of embedded software. The proposed technique is ...
Weidong Wang, Anand Raghunathan, Ganesh Lakshminar...
ICS
2007
Tsinghua U.
14 years 1 months ago
Scheduling FFT computation on SMP and multicore systems
Increased complexity of memory systems to ameliorate the gap between the speed of processors and memory has made it increasingly harder for compilers to optimize an arbitrary code...
Ayaz Ali, S. Lennart Johnsson, Jaspal Subhlok
MICRO
2000
IEEE
72views Hardware» more  MICRO 2000»
13 years 7 months ago
PipeRench implementation of the instruction path coprocessor
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...
TPDS
1998
124views more  TPDS 1998»
13 years 7 months ago
Using Recorded Values for Bounding the Minimum Completion Time in Multiprocessors
—The way the processes in a parallel program are scheduled on the processors of a multiprocessor system affects the performance significantly. Finding a schedule of processes to ...
Lars Lundberg, Håkan Lennerstad