We have proposed (, )-based flow regulation to reduce delay and backlog bounds in SoC architectures, where bounds the traffic burstiness and the traffic rate. The regulation is co...
Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, Mohamma...
This paper proposes a new methodology to model the distribution of finite size content to a group of users connected through an overlay network. Our methodology describes the distr...
Stochastic device noise has become a significant challenge for high-precision analog/RF circuits, and it is particularly difficult to correctly include both white noise and flic...
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....