Sciweavers

126 search results - page 16 / 26
» Space Based Architecture for Numerical Solving
Sort
View
DATE
2010
IEEE
122views Hardware» more  DATE 2010»
14 years 23 days ago
Optimal regulation of traffic flows in networks-on-chip
We have proposed (, )-based flow regulation to reduce delay and backlog bounds in SoC architectures, where bounds the traffic burstiness and the traffic rate. The regulation is co...
Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, Mohamma...
TPDS
2008
96views more  TPDS 2008»
13 years 8 months ago
Stochastic Graph Processes for Performance Evaluation of Content Delivery Applications in Overlay Networks
This paper proposes a new methodology to model the distribution of finite size content to a group of users connected through an overlay network. Our methodology describes the distr...
Damiano Carra, Renato Lo Cigno, Ernst W. Biersack
DAC
2011
ACM
12 years 8 months ago
Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials
Stochastic device noise has become a significant challenge for high-precision analog/RF circuits, and it is particularly difficult to correctly include both white noise and flic...
Fang Gong, Hao Yu, Lei He
CF
2004
ACM
14 years 1 months ago
A first glance at Kilo-instruction based multiprocessors
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
Marco Galluzzi, Valentin Puente, Adrián Cri...
VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
14 years 8 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar