Sciweavers

47 search results - page 6 / 10
» Special Issue: Current Trends in Compilers for Parallel Comp...
Sort
View
DATE
2009
IEEE
104views Hardware» more  DATE 2009»
14 years 1 months ago
Programming MPSoC platforms: Road works ahead!
Abstract—This paper summarizes a special session on multicore/multi-processor system-on-chip (MPSoC) programming challenges. The current trend towards MPSoC platforms in most com...
Rainer Leupers, Andras Vajda, Marco Bekooij, Soonh...
APCSAC
2001
IEEE
13 years 10 months ago
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
Kenji Watanabe, Wanming Chu, Yamin Li
PDP
2010
IEEE
13 years 5 months ago
FTDS: Adjusting Virtual Computing Resources in Threshing Cases
—In the virtual execution environment, dynamic computing resource adjustment technique, configuring the computing resource of virtual machines automatically according to the actu...
Jian Huang, Hai Jin, Kan Hu, Zhiyuan Shao
ICS
2001
Tsinghua U.
13 years 11 months ago
Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., imp...
Chong-liang Ooi, Seon Wook Kim, Il Park, Rudolf Ei...
SPAA
2006
ACM
14 years 1 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...