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» Speculative Computation in Multilisp
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IPPS
2006
IEEE
14 years 2 months ago
Improving cache locality for thread-level speculation
With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising technique for exploiting this highly multithreaded hardware to improve the perfo...
Stanley L. C. Fung, J. Gregory Steffan
PPOPP
2003
ACM
14 years 1 months ago
Using thread-level speculation to simplify manual parallelization
In this paper, we provide examples of how thread-level speculation (TLS) simplifies manual parallelization and enhances its performance. A number of techniques for manual parallel...
Manohar K. Prabhu, Kunle Olukotun
HPCA
2003
IEEE
14 years 8 months ago
Power-Aware Control Speculation through Selective Throttling
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...
Juan L. Aragón, José González...
DAC
2003
ACM
14 years 9 months ago
Power-aware issue queue design for speculative instructions
Speculatively issued instructions may be particularly sensitive to increases in pipeline depth. Our results indicate that as pipeline depth increases, speculation increases the pe...
Tali Moreshet, R. Iris Bahar
SBACPAD
2003
IEEE
75views Hardware» more  SBACPAD 2003»
14 years 1 months ago
The Limits of Speculative Trace Reuse on Deeply Pipelined Processors
Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ...
Maurício L. Pilla, Amarildo T. da Costa, Fe...