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» Speculative Parallel Threading Architecture and Compilation
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ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 18 days ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
ICPPW
2009
IEEE
14 years 2 months ago
Hardware Microkernels for Heterogeneous Manycore Systems
Abstract— The migration away from power-hungry, speculative execution procesors towards manycore architectures is good news for the embedded and real-time systems community. Comm...
Jason Agron, David L. Andrews
PPOPP
2010
ACM
14 years 5 months ago
Does cache sharing on modern CMP matter to the performance of contemporary multithreaded programs?
Most modern Chip Multiprocessors (CMP) feature shared cache on chip. For multithreaded applications, the sharing reduces communication latency among co-running threads, but also r...
Eddy Z. Zhang, Xipeng Shen, Yunlian Jiang
IPPS
2007
IEEE
14 years 2 months ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
FIDJI
2003
Springer
14 years 27 days ago
Hard Real-Time Implementation of Embedded Software in JAVA
The popular slogan ”write once, run anywhere” effectively renders the expressive capabilities of the Java programming framework for developing, deploying, and reusing target-i...
Jean-Pierre Talpin, Abdoulaye Gamatié, Davi...