Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
— L1 data caches in high-performance processors continue to grow in set associativity. Higher associativity can significantly increase the cache energy consumption. Cache access...
Dan Nicolaescu, Babak Salamat, Alexander V. Veiden...
We present Zyzzyva, a protocol that uses speculation to reduce the cost and simplify the design of Byzantine fault tolerant state machine replication. In Zyzzyva, replicas respond...
Ramakrishna Kotla, Lorenzo Alvisi, Michael Dahlin,...
A read-only transaction (ROT) does not modify any data. Efforts are being made in the literature to improve the performance of ROTs without correctness and data currency issues. T...
Linearizability is a key design methodology for reasoning about tations of concurrent abstract data types in both shared memory and message passing systems. It provides the illusi...