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ICS
2007
Tsinghua U.
14 years 1 months ago
An L2-miss-driven early register deallocation for SMT processors
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
Joseph J. Sharkey, Dmitry V. Ponomarev
IEEEPACT
2000
IEEE
14 years 1 days ago
On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors
In this paper, we look at two issues which could affect the performance of value prediction on wide-issue ILP processors. One is the large number of accesses to the value predicti...
Sang Jeong Lee, Pen-Chung Yew
ICS
1998
Tsinghua U.
13 years 12 months ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...
COMPUTER
1998
68views more  COMPUTER 1998»
13 years 7 months ago
Making Network Interfaces Less Peripheral
Much of a computer’s value depends on how well it interacts with networks. To enhance this value, designers must improve the performance of networks delivered to users. Fortunat...
Shubhendu S. Mukherjee, Mark D. Hill
ICML
2008
IEEE
14 years 8 months ago
Memory bounded inference in topic models
What type of algorithms and statistical techniques support learning from very large datasets over long stretches of time? We address this question through a memory bounded version...
Ryan Gomes, Max Welling, Pietro Perona