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ICC
2007
IEEE
115views Communications» more  ICC 2007»
14 years 19 days ago
Super-Wideband SSN Suppression in High-Speed Digital Communication Systems by Using Multi-Via Electromagnetic Bandgap Structures
With the advance of semiconductor manufacturing, There are many approaches to deal with these problems. EDA, and VLSI design technologies, circuits with even higher Adding discrete...
MuShui Zhang, YuShan Li, LiPing Li, Chen Jia
ISMB
1994
13 years 10 months ago
High Speed Pattern Matching in Genetic Data Base with Reconfigurable Hardware
Homologydetection in large data bases is probably the most time consuming operation in molecular genetic computing systems. Moreover, the progresses made all around the world conc...
Eric Lemoine, Joël Quinqueton, Jean Sallantin
HPCA
2011
IEEE
13 years 15 days ago
A new server I/O architecture for high speed networks
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
Guangdeng Liao, Xia Znu, Laxmi N. Bhuyan
FPL
2007
Springer
140views Hardware» more  FPL 2007»
14 years 2 months ago
An area-efficient alternative to adaptive median filtering in FPGAs
This paper presents a new approach to the FPGA implementation of image filters which are utilized to remove the saltand-pepper noise of high intensity (up to 70% of corrupted pix...
Zdenek Vasícek, Lukás Sekanina
VISSYM
2003
13 years 10 months ago
Smart Hardware-Accelerated Volume Rendering
For volume rendering of regular grids the display of view-plane aligned slices has proven to yield both good quality and performance. In this paper we demonstrate how to merge the...
Stefan Röttger, Stefan Guthe, Daniel Weiskopf...