1186 search results - page 26 / 238 » State machine models of timing and circuit design |
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
We present a methodology for generating black-box timing models for full-custom transistor-level CMOS circuits. Our approach utilizes transistor-level ternary symbolic timing simu...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
In this paper, a new approach to analog test design based on the circuit design process, called Characteristic Observation Inference (COI), is presented. In many situations, it is...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Traditional implementation...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. U...
SPAA
2005
ACM
14 years 1 months ago
2005
ACM
We study the problem of asymptotically reducing the runtime of serial computations with circuits of polynomial size. We give an algorithmic size-depth tradeoff for parallelizing ...